1. Technical Field
This invention relates in to a field effect device having a channel of carbon nanofabric, a static ram made of such, and a method of making the same.
2. Discussion of Related Art
Static RAM (SRAM) memory, both stand alone and embedded, requires increasingly dense cells with every technology generation, increased performance, and lower leakage currents. Six transistor SRAM cells may be designed for very low power operation including very low leakage currents. Six transistor SRAM cells may also be designed for high performance applications, such as cache memory, with higher leakage tolerance, but still requiring low leakage currents.
Six transistor SRAM cells comprise two NFET cell access transistors, as well as two NFET pull-down devices and two PFET pull-up (load) devices, all co-planar, and cross coupled to form a flip flop storage cell as is well known in the semiconductor industry. Stacking of load devices can reduce SRAM cell size (area) by 30 to 50%. Stacking of load devices has been used in earlier generations of SRAMs for density enhancement. For example, stacking of SRAM cell load devices using polysilicon resistors has been used to shrink cell size. However, stacked poly load resistors are no longer used in new SRAM products because of high leakage currents due to poor scalability, and because polyresistors always conduct current. Stacked thin film PFET devices were also tried in earlier SRAM generations, however, such stacked thin film PFETs are no longer used due to high leakage currents and poor scalability.
FIG. 1 illustrates a schematic of a prior art coplanar six device SRAM memory cell 100, including storage cell 110 and connections to word line WL, bit lit BL, and complimentary bit line Blb (bit line-bar). Inverter 120 comprising NFET pull-down device T2 and PFET pull-up (load) device T3, and inverter 130 comprising NFET pull-down devices T4 and P-FET pull-up device T5 are interconnected in the conventional manner (“cross coupled”) to form a flip flop storage cell. Transfer devices T1 and T6 connect are connected to both inverters 120 and 130 to form memory cell 110, and also connected to array lines WL, BL and BLb, in the conventional manner. Basic SRAM cell and chip operation is described in K. Itoh, “VLSI Memory Chip Design,” Springer Publishing, 2001, pp. 26-31.